Experimenting with MyHDL

MyHDL is a very good tool to convert python code to VHDL or Verilog. It can encapsulate a user from writing VHDL and Verilog codes. Since I am using Python for years, I opt to reuse it instead of learning VHDL or Verilog. Just to share, I tried to create a simple project using Altera Quartus as an experiment.

Here is a simple code in python.

The output in VHDL is here.

The resulting RTL from Quartus:



I was impressed because MyHDL is smart enough to recognize if a pin is used as an output or input.