Hierarchial Design using MyHDL

My aim today is to learn modular style of programming to MyHDL for reusability purpose. I am trying to implement multiple instances in a single VHDL file and I find it easy to implement using MyHDL.

Here is the python script.

Here is the resulting VHDL file.

Here is the resulting RTL schematic from Quartus II

Experimenting with MyHDL

MyHDL is a very good tool to convert python code to VHDL or Verilog. It can encapsulate a user from writing VHDL and Verilog codes. Since I am using Python for years, I opt to reuse it instead of learning VHDL or Verilog. Just to share, I tried to create a simple project using Altera Quartus as an experiment.

Here is a simple code in python.

The output in VHDL is here.

The resulting RTL from Quartus:



I was impressed because MyHDL is smart enough to recognize if a pin is used as an output or input.